There exists a need for a flexible, sheet-like composite article which has large scale predictable dimensional stability. That is, a significant segment of the article should have the ability to avoid substantial unpredictable dimensional alteration after being subjected to extreme conditions such as heat, cold and moisture upon return to ambient conditions. Such products will undergo only minor predictable variation in dimension when subjected to such environmental conditions. Predictability refers to the expected change in dimensions based on an understanding of inherent properties of materials to irreversibly shrink or expand after exposure to certain environmental conditions and return to ambient conditions.
Products of this type find utility in such fields as photolithography, the manufacture of flexible circuitry, etching, plating, and vapor deposition. Other utilities include the manufacture of “egg crate” substrates for gyricon rotating-particle displays as disclosed in U.S. Pat. No. 5,815,306 (Sheridon, et al.).
Such predictably dimensionally stable composite articles should meet the dimensional stability requirements for fine-pitch electronic circuits. Fine pitch electronic circuits find applicability in electronic chip packaging, i.e., so-called “first-level” packaging as the intermediary between the silicon chip and other external circuitry. Fine pitch electronic circuits are also used as printed circuit boards to which pre-packaged chips are attached, and other electronic interconnect devices, especially where minimization of component size and/or weight are important.
The so-called Built-Up Multilayer (BUM) process, used for packaging and connecting electronic chips, starts with a core, typically metal foil laminated to both sides of a dielectric layer, or metal deposited onto the dielectric core. The BUM process is practiced in several versions, differentiated by the techniques used for applying successive layers of dielectric and metal, and by the techniques used to define the vias. See, for example, Charles E. Bauer, “Using Chip Scale Packages,” Advanced Packaging 5 (4), July/August 1996, pp. 8-10; Howard Green and Phillip Garrou, “Introduction to Large Area Substrate Processing,” Advancing Microelectronics 24 (2), March/April 1997, pp. 10-15; Charles Lassen, “Build-Up Multilayers,” Printed circuit Fabrication 20 (6), June 1997, pp. 22-24; and Darren Hitchcock, “Microvias, High Speed, and Flex,” Proc. IPC Natl. Conf. on Flexible Circuits, May 19-20, 1997 (Phoenix, Ariz.). Via formation technologies in common practice include: direct photolithographic patterning of photosensitive dielectrics, pattern-wise laser ablation, and chemical milling or plasma ablation through patterned resist or metallization.
A common shared element is the need to have a predictably dimensionally stable substrate, so that the patterning of the several layers of material in the multilayer structure (dielectric and metal) will be aligned layer to layer. To achieve nominal 25 μm line and 25 μm space, as would be required for chip-scale packaging, the individual layers of patterned metallization and of vias (holes) in the dielectric need to be aligned to better than ±50% the spacing, i.e., better than ±12.5 μm to an absolute reference point (fiducial mark). The core or base material upon which the multilayers are built needs to have dimensional stability at least this good, if not better. The preparation of larger scale predictably dimensionally stable composite articles provides the way to reduce the per unit cost of products made from smaller segments of such articles.
Identification of Related Art
The following references are relevant to the invention:                U.S. Pat. No. 3,689,346 (Rowland);        U.S. Pat. No. 4,576,850 (Martens);        U.S. Pat. No. 4,414,316 (Conley);        U.S. Pat. No. 5,175,030 (Lu and Williams);        WO9015673 (Kerr and Crouch);        EP-130659 (Brown); and        U.S. Pat. No. 4,810,435 (Kamada, et al.)        